A capacity of a dynamic random access memory (DRAM) used as a main memory of a computer has recently approached the limit. On the other hand, as represented by analysis of big data and machine learning, a demand for processing large capacities of data at high speed by in-memory computing is increasing.
In an application using a huge memory space, researches are conducted to extend the memory space using a next generation nonvolatile memory. The next generation nonvolatile memory is, for example, a NAND flash memory and may be a low speed and large capacity memory. The next generation nonvolatile memory may be used in combination with a high-speed small-capacity memory such as DRAM.
A cache server including the DRAM and the NAND flash memory has a problem that the unit price per capacity of the DRAM is high and the power consumption is large. If the memory space of the cache server is expanded using the NAND flash memory of which the capacity unit price is cheaper than that of the DRAM, the cost problem is solved. However, the NAND flash memory has a speed which is about three orders of magnitude lower than the DRAM. Therefore, in the cache server, in order to achieve both high speed and low price, it is assumed that the DRAM and the NAND flash memory are separately used appropriately.
FIG. 1 is a diagram illustrating an example of a change in latency in the DRAM and the NAND flash memory. In FIG. 1, a horizontal axis represents a data size (kilobytes; KB), and a vertical axis represents the latency (nanoseconds; ns).
In the example illustrated in FIG. 1, a change in the latency of the DRAM (A1) when the data size is increased is smaller than a change in the latency of the NAND flash memory (A2). The NAND and the DRAM, which are a value obtained by dividing the latency of the NAND flash memory by the latency of the DRAM, becomes smaller as the data size increases (A3). The data may be referred to as an item.
As appropriate separate use of the DRAM and the NAND flash memory, for example, separate use of the memories depending on access frequency and separate use of the memories depending on item size are assumed.
The separate use of the memories depending on access frequency may be performed by arranging frequently accessed items in the DRAM and infrequently accessed items in the NAND flash memory.
The separate use of the memories depending on access frequency is effective for workloads that are biased in access frequency.
FIG. 2 illustrates an example of the separate use of the memories depending on access frequency. In an example illustrated in (1) of FIG. 2, when storing items in an order of access frequency, a degree of popularity (which may be referred to as “access frequency”) of an item C stored in the DRAM is higher than the popularity degree of items D and E stored in the NAND flash memory.
In an example illustrated in (2) of FIG. 2, when an item stored in the NAND flash memory is read, a storage destination of the item is changed to the DRAM.
In an example illustrated in (3) of FIG. 2, when an item stored in the NAND flash memory is read out and there is no spare capacity in the DRAM for storing the item, it is assumed that the item is stored in the DRAM by pushing out an item stored in the DRAM to the NAND flash memory.
As described above, it is assumed that storage destinations of items stored in the memories having different speeds are changed. The above description is an example of the case where the storage destination of the item is changed.
The separate use of the memories depending on item size may be performed by arranging an item having a size less than a certain size in the DRAM and arranging an item having a size equal to or larger than the certain size in the NAND flash memory.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication No. 2016-170729, Japanese Patent No. 5992592, and M. Blott, L. Liu, K. Karras, and K. Vissers, “Scaling Out to a Single-Node 80 Gbps Memcached Server with 40 Terabytes of Memory HotStorage”, 2015.
However, in the separate use of the memories depending on access frequency, there is a possibility that response is deteriorated by changing the storage destination of the items arranged in the memories having different speeds.